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-- Company: 
-- Engineer:
--
-- Create Date:   23:18:27 10/05/2009
-- Design Name:   
-- Module Name:   /usa/cates/cpeg422/proj1/program_rx_tb.vhd
-- Project Name:  proj1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: program_rx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY program_rx_tb IS
END program_rx_tb;
 
ARCHITECTURE behavior OF program_rx_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT program_rx
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         data_out : OUT  std_logic_vector(127 downto 0);
         has_data : OUT  std_logic;
         rd_ack : IN  std_logic;
         rd_uart : OUT  std_logic;
         rx_empty : IN  std_logic;
         r_data : IN  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal rd_ack : std_logic := '0';
   signal rx_empty : std_logic := '0';
   signal r_data : std_logic_vector(7 downto 0) := (others => '0');

 	--Outputs
   signal data_out : std_logic_vector(127 downto 0);
   signal has_data : std_logic;
   signal rd_uart : std_logic;

   -- Clock period definitions
   constant clk_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: program_rx PORT MAP (
          clk => clk,
          reset => reset,
          data_out => data_out,
          has_data => has_data,
          rd_ack => rd_ack,
          rd_uart => rd_uart,
          rx_empty => rx_empty,
          r_data => r_data
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      wait for 100ms;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
